Responsibilities/ Tasks :

Industry Experience : 6-10years (Floorplanner Lead)o Tapeout experience in full chip floorplan/full chip partitioning flow. Experience in die-size estimation spread sheet IP based and synthesis basedo Experience in IO/Bump planning & placement, custom analog/PG planning and route implementationo Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantageo Experience in RDL routingo Experience in interfacing with cross functional teams and block PnR teamso Good understanding of basic shell scripting, tool based TCL scripting to automate all custom activitieso Experience in version control systemso Experience in managing/mentoring small teams Industry Experience : 6-10years (Clocking Lead)o Multiple tapeout experience in full chip PnR for lower node technologies.o Thorough understanding of different clocking architecture and their impact on chip performanceo Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantageo Experience in ETM/QTM based full chip PnR including synthesiso Prior experience in defining clock constraints and derates in conjunction with technology and front end design teamo Full chip CTS methodology planning/implementation.o Experience in interfacing with cross functional teams and block PnR teamso Good understanding of basic shell scripting, tool based TCL scripting to automate all custom activitieso Experience leading team of significant strength.o Experience in version control systemso Experience in managing/mentoring small teams 8+ years of hands-on experience in Static Timing analysis flows. Experience in Multi-mode/Multi-corner runs. Constraints development and management of multi partition design and top level Chip Level IO timing closure Experience in FUNC/DFT timing closure Experience in analysis of timing paths to identify key issues. Timing Convergence ( Both Inter/Intra block Level) Understanding of noise, cross-talk, OCV effects, margins, and constraints. Experience in timing and power ECO techniques and implementation Automation Skills using scripting languages like TCL/PERL/Python/SHELL Tools - Primetime/TempusIndustry Experience : 6-10years (Physical Verification Lead) Develop fullchip flows and own physical design verification, analysis & signoff in advanced technology nodes. Owned and delivered the fullchip tapeout gds requirements for one or more designs. Must have experience in TSMC/Intel 16/10nm technology node or below. Experience in analyzing and solving DPT(double/multiple patterning) loop issues. Experience in analyzing fullchip LVS, PG shorts & related issues. Debug and fixing of fullchip DRC, MRC, Antenna, latchup, ERC, PERC issues. Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality. Must have hands-on experience in Mentor Calibre/Synopsys ICV/Cadence PVS. Experience in chip integration using gds merge tools or Virtuoso. Experience in Innovus/ICC2 is good to have. Prior experience in leading a PDV team of 2-5 engineers for blocks & fullchip tapeout closure.Industry Experience : 6-10years (Reliability [EM/IR] Verification Lead) Develop fullchip flows and own IR drop, EM analysis & signoff in advanced technology nodes. Resolve fullchip design and flow issues related to PDN (power distribution network), identify potential solutions and interface with PD team to get the change implemented. Experience in fullchip running mesh resistance, static, dynamic IR/EM checks, analyzing the results and providing solutions. Able to review design requirements and decide on vectorless simulation duration, VCD cycle selection. Ability to run Redhawk with DFT VCD patterns and provide solutions for issues. Able to generate fullchip STA timing fi

Education/certification :

• Bachelor/ technical studies

Key Skills Required :

• Technical Skills (ERS)-VLSI-Physical design-STA (Static Time Analysis)