Responsibilities/ Tasks :

Industry Experience : 6-10years (Physical Verification Lead) Develop fullchip flows and own physical design verification, analysis & signoff in advanced technology nodes. Owned and delivered the fullchip tapeout gds requirements for one or more designs. Must have experience in TSMC/Intel 16/10nm technology node or below. Experience in analyzing and solving DPT(double/multiple patterning) loop issues. Experience in analyzing fullchip LVS, PG shorts & related issues. Debug and fixing of fullchip DRC, MRC, Antenna, latchup, ERC, PERC issues. Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality. Must have hands-on experience in Mentor Calibre/Synopsys ICV/Cadence PVS. Experience in chip integration using gds merge tools or Virtuoso. Experience in Innovus/ICC2 is good to have. Prior experience in leading a PDV team of 2-5 engineers for blocks & fullchip tapeout closure.

• To be responsible for providing technical guidance or solutions
• To develop and guide the team members in enhancing their technical capabilities and increasing productivity
• To ensure process compliance in the assigned module, and participate in technical discussions or review.
• To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.

Education/certification :

• Bachelor/ technical studies

Key Skills Required :

• Technical Skills (ERS)-VLSI-Verification Methodology-UVM